For each PRESENT state, indicate the level required at each J and K input in order to produce the transition to the NEXT state. STEP -3 Add a column to this table for each J and K input. STEP -2 Use the state transition diagram to set up a table that lists all PRESENT states and their NEXT states Present state Next state C B A 1 2 3 4 5 6 7 8Ģ0 Synchronous Counter Design / Example (1) ….cont. STEP -1 Draw the state transition diagram showing all the possible states, including those that are not part of the desired counting sequenceġ9 Synchronous Counter Design / Example (1) ….cont. That mean always K=0 and J can be either level K=0 and J=X( don’t care)ĭesign Procedure Given a Counter sequence, C B A 1 etc.ġ8 Synchronous Counter Design / Example (1) This can happen either J=K=0 or J=1 and K=0. That mean always K=1 and J=0 or1 K=1 and J=X( don’t care) TRANSITION The present state is 1 and it has to change to 1. This can happen either J=0 and K=1 or J=K=1. That mean always J=1 and K=0 or1 J=1 and K=X( don’t care) TRANSITION The present state is 1 and it has to change to 0. This can happen either J=1 and K=0 or J=K=1. TRANSITION: The present state is 0 and it has to change to 1. That mean J=0 and K=0 or 1 That’s J=0 and K=X(don’t care) That can be either J=K=0 status or J=0,K=1. J-K Excitation Table TRANSITION AT OUTPUT PRESENT STATE Q(N) NEXT STATE Q(N+1) J K 1 X TRANSITION FF’s Present status is 0 and it should remain in 0 when a clock pulse is applied. J-K Excitation Table Before begin the designing we must know the operation of the J-K FF, let us analysis Truth table for 74LS76 IC (JK flip-flop) and its excitation table.ġ3 Truth table for 74LS76 IC (JK flip-flop) In synchronous counters all the FF’s are clocked at the same time. Here we will learn one common method using JK flip-Flops. Several methods are available that follow arbitrary sequence. Points where the AND gate outputs are HIGH are indicated by the shaded areas. The term Synchronous refers to events that have a fixed time relationship with each other AND receive cllock pulse from a common source 2-bit synchronous binary counter.Ĭlk pulse Q2 Q1 Q0 1 2 3 4 5 6 7 8 (REPEAT)ĬLK PLUSE Q3 Q2 Q1 Q0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REPEAT A 4-bit synchronous binary counter and timing diagram. The inputs the NAND gate are from the Q output from FF1 and FF3 ( from FF3FF2FF1FF0) CLK PLUSE Q3 Q2 Q1 Q0 1 2 3 4 5 6 7 8 9 10 GLITCH 11 12 13 14 15 16 MOD 10 RIPPLE UP COUNTER – NGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE FROM Q MOD 10 AS RESET / CLITCH AT 1010. The inputs the NAND gate are from the Q output from FF1 and FF3 ( from FF3FF2FF1FF0)Ĩ An asynchronously clocked decade counter with asynchronous recycling.Īsynchronous Decade Counter An asynchronously clocked decade counter with asynchronous recycling. One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR) inputs of the flip-flops. To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible states. Counters with the states in their sequence are called decade counters. Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The Modulus of a counter is the number of unique states that the counter will sequence through. CLK PLUSE Q3 Q2 Q1 Q0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REPEAT RIPPLE COUNTER UP – NGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE FROM Q Clk pulse Q2 Q1 Q0 1 2 3 4 5 6 7 8 (REPEAT) RIPPLE COUNTER UP – PGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE FROM Q’Ħ Four-bit asynchronous binary counter and its timing diagram.Īsynchronous/Ripple Counter Four-bit asynchronous binary counter and its timing diagram. Three-bit asynchronous binary counter and its timing diagram for one cycle. Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. Only the first FF receive clock pulse from the source ( clock genarator), others FFs receive clock pulse from either Q or Q’ of prior FF So the effect of an input clock pulse “ripples” through the counter, taking some time, due to propagation delays, to reach the last flip-flop. Cannot get to the second flip-flop (FF1) immediately because of the propagation delay through FF0. * Digital counters have the following important characteristics, Maximum number of count Up-Down Count Asynchronous or Synchronous Operation Free-Running or Self-StoppingĪsynchronous counter are commonly referred to as ripple counter because the effect of the input clock pulse is first “felt” by first flip-flop (FF0). * They are Sequential logic circuits because timing is obviously important and they need a memory characteristic. 2 Counters * Counters are important digital electronic circuits.
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